GTC: architecture exploration for generation-in-time computing paradigm

Pengju Ren; Gelin Fu; Shenghuan Liu; Yadong Zhang; Qiwei Dang; Tian Xia; Wenzhe Zhao; Nanning Zheng

doi:10.59717/ipj.aiplus.2026.100007

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GTC: architecture exploration for generation-in-time computing paradigm

1.
National Key Laboratory of Human-Machine Hybrid Augmented Intelligence, Xi'an Jiaotong University, Xi'an 710049, China
2.
Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University, Xi'an 710049, China

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Corresponding author: *Correspondence: pengjuren@xjtu.edu.cn
Received Date: May 11, 2026

Accepted Date: August 15, 2026

Published Online: August 18, 2026

AI Plus https://doi.org/10.59717/ipj.aiplus.2026.100007 | Cite this article

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1. Devices often store many predefined programs even when only one task is active at a time.
  
  Generation-in-Time Computing (GTC) builds context-specific machine-code streams before edge execution.
  
  GTC cuts dynamic instructions by 68.8% and FPGA logic power by 52.7% in a path-planning case study.
  
  GTC is especially promising for robots, sensors, and IoT systems that must adapt quickly to changing contexts.

ABSTRACT

ABSTRACT

We propose Generation-in-Time Computing (GTC), a software-hardware co-design paradigm in which a centralized, large language model-based generation system translates real-time physical context and target hardware constraints into task-specific executable instruction streams. To realize this paradigm, we present Arch-X, a computation-centric edge architecture that exploits these specialized streams by eliminating or simplifying complex microarchitectural structures commonly used in high-performance processors. We evaluate GTC on three workloads: LLM-guided A* path planning, breadth-first search (BFS), and TinyEKF sensor fusion. For LLM-guided A*, GTC reduces the number of dynamic instructions by 68.8% and branch instructions by 81.9% relative to a predefined-computing baseline. Across all three workloads, GTC improves performance on both in-order and out-of-order processors. An FPGA implementation further shows that Arch-X reduces lookup-table (LUT) and block-RAM (BRAM) usage by 71.1% and 86.2%, respectively, relative to a dual-issue out-of-order reference core, while retaining the arithmetic datapath required by the evaluated workloads. Together, these results provide preliminary evidence that resolving context-dependent control through centralized generation can reduce software overhead and enable simpler edge hardware for efficient, adaptive computation.
- large language model /
- computing system /
- processor

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Ren P., Fu G., Liu S., et al. (2026). GTC: architecture exploration for generation-in-time computing paradigm. AI Plus 1:100007. https://doi.org/10.59717/ipj.aiplus.2026.100007

Ren P., Fu G., Liu S., et al. (2026). GTC: architecture exploration for generation-in-time computing paradigm. AI Plus 1:100007. https://doi.org/10.59717/ipj.aiplus.2026.100007

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GTC: architecture exploration for generation-in-time computing paradigm

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