Huawei proposes “τ Scaling Law” as a post-Moore framework for semiconductor development

On May 25, China's telecommunications giant Huawei announced a new concept called the τ(time) Scaling Law on its official website following the 2026 International Symposium on Circuits and Systems, organized by IEEE, one of the world’s leading engineering organizations. The keynote, titled “New Semiconductor Path in Practice: τ Scaling Law for the Post-Moore Era,” was delivered by Huawei Director and Head of its Semiconductor Business Group, He Tingbo.

The proposal arrives as the semiconductor industry continues to grapple with the slowdown of Moore’s law, a 61-year-old observation that predicted that the number of transistors on an integrated circuit tends to double approximately every 2 years, leading to a rapid increase in computing power and a decrease in cost per transistor. As transistor sizes shrink toward atomic scales, quantum tunneling, leakage currents, and heat dissipation now impose fundamental limits on conventional scaling approaches.

The τ Scaling Law proposes a shift away from traditional “geometric scaling” toward “temporal scaling,” which focuses on reducing time delays in computation and signal transmission across semiconductor systems. At the center of the τ Scaling Law is the idea that future performance gains will come less from how small transistors can be made and more from how efficiently systems manage time. In this model, the key metric becomes the time constant (τ), representing delays in signal propagation and processing across devices, circuits, chips, and full computing systems.

He Tingbo contends that as physical scaling slows, time-based optimization offers a new frontier for continued performance improvement. Instead of relying primarily on increasing transistor density through smaller manufacturing nodes, engineers would focus on reducing latency at every stage of computation.

A major technical pillar of the τ Scaling Law is a set of techniques Huawei calls “logic folding.” This approach restructures how computational logic is physically implemented on silicon. Rather than relying on traditional flat layouts, logic folding compresses and reorganizes circuit paths to reduce signal travel distances and improve execution speed.

At the device level, Huawei says the approach involves optimizing transistor structures and interconnects to minimize resistance and parasitic capacitance, both of which contribute to signal delay. At the circuit level, it reduces physical routing complexity, shortening critical paths that limit performance.

At the chip level, the framework emphasizes “software-architecture-hardware co-design,” aligning instruction execution and data movement more closely with real workload patterns. This approach enables finer-grained control of instruction flow, improved parallelism, and more efficient use of hardware resources.

At the system level, Huawei highlights a new interconnect architecture, designed to enable unified memory addressing and native memory semantics across multiple computing nodes. The company claims this could significantly reduce communication latency in large-scale distributed computing systems, which has become a growing bottleneck in artificial intelligence workloads.